1. Field of the Invention
This invention relates to an I/O interface circuit capable of carrying out rapid data transmission, a semiconductor chip having this I/O interface circuit and a semiconductor system provided with a plurality of the semiconductor chips.
2. Description of the Prior Art
In recent years, the performance of high-performance LSI such as a micro processor has been rising rapidly. This rise of the performance is supported by application of high frequency internal clock by process scaling or introduction of pipeline method.
On the other hand, currently, signal transmission between semiconductor chips cannot meet this application of high frequency internal clock inside the semiconductor chip sufficiently. In a conventional TTL/LV-TTL I/O interface, signal transmission with high frequency wave of more than 100 MHz is difficult to realize due to crosstalk, simultaneous signal switching noise (SSN), reflection of signal in transmission path and the like. Therefore, the TTL/LV-TTL interface and the like is a bottleneck of the performance of a high performance LSI.
If the signal transmission speed between the semiconductor chips is not increased, a trend of multiple pins is indispensable for securing a band width, so that this largely influence production, mounting work, and board cost. Therefore, in the high-performance LSI field, an I/O interface capable of high speed signal transmission has been introduced gradually.
FIGS. 1A-1C show a TTL/LV-TTL I/O interface which has been generally used in a conventional art. FIG. 1A is a structure diagram thereof, FIG. 1B is a potential waveform diagram upon xe2x80x9cHxe2x80x9d level transmission, and FIG. 1C is a current waveform diagram upon xe2x80x9cHxe2x80x9d level transmission.
When for example, xe2x80x9cHxe2x80x9d level is transmitted from a semiconductor chip 110 of TTL to a semiconductor chip 120 of LV-TTL through a transmission path 101, P channel MOSFET 112 and N channel MOSFET 113 constituting an I/O buffer 111 of the semiconductor chip 110 are both turned on. As a result, current flowing through the transmission path 101 changes as shown in FIG. 1C and with an convergence of current amount, the potential is stabilized on VDDQ level as shown in FIG. 1B. Then, on the side of the semiconductor chip 120, the xe2x80x9cHxe2x80x9d level signal of the transmission path 101 is received by a differential amplifier 121.
Because the side of the semiconductor chip 120 in input mode becomes an open end in this I/O interface, signal reflection occurs in the transmission path 101 so that transmission waveform is distorted. Further, because the logical amplitude is large, noise due to dI/dt occurs in high speed operation. Thus, in the high speed I/O interface, generally, the transmission path is terminated.
FIGS. 2A-2E show high speed interface circuits of conventional various terminating types. FIG. 2A shows a GTL/RSL interface, FIG. 2B shows a push-pull type HSTL interface, FIG. 2C shows a SSTL interface, FIG. 2D shows a CTT interface and FIG. 2E shows a LVDS interface.
Because terminating resistors 201, 301, 401, 501, 601 are mounted on a board in the vicinity of the second semiconductor chip 2, if signal is transmitted from the first semiconductor chip 1 to the second semiconductor chip 2, signal reflection at a buffer portion of the second semiconductor chip 2 in input mode is suppressed. Further, because dI/dt can be set small as well as the logical amplitude is small, there does not occur much noise.
FIG. 3 is a structure diagram showing a conventional high-speed interface circuit disclosed in Japanese Patent Application Laid-Open No.8-204539.
In the same Figure, reference numeral 710 denotes a transmission path, numerals 711-714 denote a terminating resistor, numerals 720, 730, 740, 750 denote a semiconductor chip, numeral 731 denotes a resisting element control means, and numerals 732, 733 denote an on chip terminating means comprising N-MOSFET.
Because in an open drain I/O interface circuit, a large reflection occurs in the transmission path when that circuit is driven from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, in this example, the signal sending side is driven by a push-pull buffer (on chip terminating resistor means 732, 733) complementarily so as to keep the sending side chip end of the transmission path 710 from being open.
However, the above first conventional I/O interface circuit has such a problem that a terminating resistor is required to be provided on the board to prevent reflection by an open end thereby producing a high cost.
Although in the respective examples shown in FIGS. 2A-2E, the description is made on an assumption of transmission of a signal in a single direction between two semiconductor chips, in case of both-way transmission of a signal between two semiconductor chips, the terminating resistor is required to be inserted in the vicinity of each semiconductor chip (parallel termination). This reason is that if signal transmission is carried out from the second semiconductor chip 2 to the first semiconductor chip 1, the side of the first semiconductor chip 1 becomes an open end so that a distortion of waveform due to reflection occurs. In such a parallel termination, in the conventional example, two terminating resistors are needed on the board.
Further, in an ordinary system, as well as a point-to-point connection shown in the conventional example, branch/stub connections each having a branch in transmission path have been widely used. In this case, if the parallel termination is carried out to prevent reflection by the open end, in the conventional example, a same number of terminating resistors as that of semiconductor chips are required to be mounted on the board.
In the aforementioned patent case, the terminating resistors 711-714 on the transmission path cannot be removed.
As described above, if it is intended to realize a high speed I/O interface circuit with terminating system according to the conventional art, it is necessary to provide the terminating resistors on the board. Thus, there is a problem in system cost and the like.
Accordingly, the present invention has been made to solve the above problem, and therefore an object of the invention is to provide a low cost I/O interface circuit not necessitating the provision of terminating resistor on a board. Another object of the present invention is to provide a semiconductor chip capable of automatically performing impedance matching between the push-pull buffer and transmission path, and a semiconductor system loaded with a plurality of the semiconductor chips.
To achieve the above object, there is provided an I/O interface circuit comprising a push-pull output buffer having: a first driving element connected between an I/O node connected to an external circuit through a transmission path and a first potential node to which a first potential is applied; and a second driving element connected between a second potential node to which a second potential is applied and the I/O node, wherein on/off status of the first and second driving elements are controlled corresponding to an input mode for inputting a signal from the external circuit and an output mode for outputting a signal to the external circuit through the transmission path, the I/O interface circuit being further so constructed that the first or second potential is terminal potential and when the input mode is selected, a driving element connected to a potential node to which the terminal potential is applied, of the first and second driving elements, is controlled so as to be turned on.
According to the first aspect of the invention, because the driving element connected to the potential node to which the terminating potential of the push-pull output buffer in input mode is applied is controlled so as to be always on, the driving element acts as a terminating element on the transmission path thereby absorbing a reflection of a signal on the transmission path.
Further, to achieve the above object, there is provided an I/O interface circuit comprising: a push-pull output buffer supplied with first and second potentials and having an output node connected to an external circuit through a transmission path; and a switch element connected between the output node of the push-pull output buffer and a third potential which is a terminal potential, wherein when input mode for inputting a signal from the external circuit through the transmission path is selected, the switch element is controlled so as to be turned on.
According to the second aspect of the invention, because the switch connected to the terminal potential is controlled so as to be on when input mode is selected, the transmission path is terminated thereby a reflection of a signal on the transmission path being absorbed.
Further, to achieve the above object, there is provided an I/O interface circuit comprising: first and second push-pull buffers each supplied with first and second potentials and each having output node connected to an external circuit through first and second transmission paths; a switch element connected between output nodes of the first and second push-pull output buffers, wherein when input mode for inputting a signal from the external circuit through the first and second transmission paths is selected, the switch element is controlled so as to be turned on.
According to the third aspect of the invention, because the switch element connected between the output nodes of the two push-pull output buffers is controlled so as to be on when input mode is selected, the transmission path is terminated thereby a reflection of signal on the transmission path being absorbed.
Further, to achieve the above object, there is provided a semiconductor chip comprising: the I/O interface circuit according to the first aspect; a replica of the push-pull output buffer according to the first aspect; an impedance element on a board, connected between an external pin connected to an output end of the replica and the second potential; a first element impedance determining means for comparing a potential appearing in the external pin to which the impedance element is connected, with an output logic potential of the reference potential generating circuit and for determining an impedance value of the first driving element in the push-pull output buffer according to a result of the comparison; and a second element impedance determining means for comparing an output logic potential of the transmission path with the output logic potential of the reference potential generating circuit and for determining an impedance value of the second driving element in the push-pull output buffer according to a result of the comparison.
According to the fourth aspect, an impedance value of a first driving element in the push-pull output buffer is determined using an impedance element on the board, connected between the external pin and second potential. Further, an output logical potential of the transmission path is monitored and an impedance value of a second driving element in the push-pull output buffer is determined. As a result, an impedance value of a driving element of the push-pull output buffer can be controlled so as to generate an appropriate output potential.
According to a preferred embodiment of the present invention, an impedance.of the impedance element is equal to an impedance of the transmission path.
Further, to achieve the above object, there is provided a semiconductor system comprising: a plurality of semiconductor chips according to the fourth aspect, connected through the transmission path; and a control means for controlling an output impedance of the plurality of the semiconductor chips according to the fourth aspect so as to match with an impedance of the transmission path.
According to a preferred embodiment of the present invention, the control means is a sequencer for executing impedance matching at the time of boot and at a predetermined time.
Further, to achieve the above object, there is provided a semiconductor chip comprising: the I/O interface circuit according to the second aspect; a replica of the push-pull output buffer according to the second aspect; a reference potential generating circuit for generating an output logic potential; an impedance element on a board, connected between an external pin connected to an output end of the replica and the second potential; a first element impedance determining means for comparing a potential appearing in the external pin to which the impedance element is connected, with an output logic potential of the reference potential generating circuit and for determining an impedance value of a driving element connected to a potential node supplied with the first potential in the push-pull output buffer according to a result of the comparison; and a second element impedance determining means for comparing an output logic potential of the transmission path with an output logic potential of the reference potential generating circuit and for determining an impedance value of a driving element connected to a potential node supplied with the second potential in the push-pull output buffer according to a result of the comparison.
According to the sixth aspect of the invention, in the interface state of the second aspect, the same impedance automatic adjustment function as the fourth aspect is exerted.
According to a preferred embodiment of the invention, the impedance of the impedance element is equal to an impedance of the transmission path.
Further, to achieve the above object, there is provided a semiconductor system comprising: a plurality of semiconductor chips according to the sixth aspect, connected through the transmission path; and a control means for controlling an output impedance of the plurality of the semiconductor chips according to the sixth aspect so as to match with an impedance of said transmission path.
According to a preferred embodiment of the invention, the control means is a sequencer for executing impedance matching at the time of boot and at a predetermined time.
Further, to achieve the above object, there is provided a semiconductor chip comprising: the I/O interface circuit according to the third aspect; a replica of the first and second push-pull output buffer according to the third aspect; a reference potential generating circuit for generating an output logic potential; an impedance element on a board, inserted between an external pin connected to an output end of the replica and said second potential; and an element impedance determining means for comparing a potential appearing in the external pin to which the impedance element is connected, with an output logic potential of the reference potential generating circuit and for determining an impedance value of a driving element connected to a potential node supplied with the first potential in the first and second push-pull output buffers according to a result of the comparison.
According to the eight aspect of the invention, in the interface state of the third aspect, the same impedance automatic adjustment function as the fourth aspect is exerted.
According to a preferred embodiment of the present invention, an impedance of the impedance element is equal to an impedance of the transmission path.
Further, to achieve the above object, there is provided a semiconductor system comprising: a plurality of semiconductor chips according to the eighth aspect, connected through the transmission path; and a control means for controlling an output impedance of the plurality of the semiconductor chips according to the eighth aspect so as to match with an impedance of the transmission path.
According to a preferred embodiment of the invention, the control means is a sequencer for executing impedance matching at the time of boot and at a predetermined time.
The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.